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FPGA Sequencer Repeater Controller


This project has a long history; first appearing in a discrete form as early as 1987, now integrated into a single chip version on a MAX 10 FPGA. The design makes use of an internal A/D converter in the chip to digitize audio and has a built in DTMF decoder using a Goertzel Algorithm. It was also a feature article in CQ Amateur Radio in December of 2016.

This implentation is realized on an EK10M08 evaluation board, which is available off the shelf. It features the standard Arduino-style headers, and a mezzanine (shield) card has been developed which buffers the receive and transmit audio, provides connections for carrier detect and push-to-talk for the repeater radios and a regulator for the 5V power supply.

The microsequencer code is developed usign a custom editor program which is then included in the flash memory of the FPGA. A set of uncommitted I/O pins can be utilized for controller other features such as link transceivers, which can be enabled by entering a DTMF sequence.